Vigenère Cipher Encryption and Decryption Implementation using Verilog

Summary:

This project focuses on implementing the Vigenère Cipher polyalphabetic substitution algorithm at the hardware level using Verilog. It transitions the cipher into a Register Transfer Level (RTL) architecture featuring modular encryption, decryption, and flexible key-management components. Data flow and modulo-26 arithmetic are controlled by an FSM.

Aim:

The aim of this project is to design, implement, and verify a hardware-level Vigenère Cipher cryptographic core using Verilog RTL. It focuses on developing an FSM-controlled architecture with a flexible key-management unit and validating its functional correctness through simulation.

Literature Survey and Technologies Used:

HDL: Verilog

FSM: Finite State Machine

Modulo 26-Arithmetic units

Methodology:

The hardware implementation of the Vigenère Cipher is divided into the basic mathematical math used and the specific Verilog modules that make up the system.

Core Mathematical Logic

• Character Mapping: Every letter from A to Z is converted into a number from 0 to 25 (A=0, B=1, ..., Z=25). Since 25 is the highest number, a 5-bit wire width is used to carry the data without losing bits.
• Encryption: The 5-bit plaintext number is added to the 5-bit key number. A modulo-26 operation is applied to keep the final result within the 0–25 alphabet range:
• {EncryptedText} = ({PlainText} + {Key}) mod 26
• Decryption: The key value is subtracted from the encrypted text value. To prevent errors or negative numbers in hardware, 26 is added before taking the modulo:
• {DecryptedText} = ({EncryptedText} - {Key}) mod 26

Vigenère Cipher

Hardware Module Description

The system is split into four distinct blocks connected under a single top-level module:

A. Vigenère Core (vigenere_core)

This block takes one plaintext character, one key character, and a mode selection signal. To avoid underflow errors during subtraction, it temporarily extends the characters to 6 bits. It then gives the output as either the encrypted or decrypted character based on the chosen mode.

B. Input Controller (input_controller)

This block takes user inputs from physical hardware switches and stores them. When the store pulse signal is high, it checks the input_mode_switch to save the incoming character as either plaintext or key data while incrementing the respective string length tracker.

C. Cipher Engine (cipher_engine)

This is the main control unit that handles the sequencing loop. When the start signal is pulsed, it runs character-by-character through the stored text flat array. If the plaintext is longer than the key, it cycles the key index back to 0 so the keyword repeats over and over until processing is finished and the done flag goes high.

D. Output Controller (output_controller)

This block manages how the final result is read out. When the cipher finishes (done == 1), the first encrypted/decrypted character is immediately displayed. Each subsequent press of the next button advances the index and displays the next character from the flat result array. Once the index reaches text_len (i.e. past the last character), the sentinel 5'b11111 is output to signal end-of-string, and then it is warped back.

Results:

The text SECRETMESSAGE was encrypted using the key KRYPTOS, and when decrypting the encrypted text CVAGXHEOJQPZS using the same key, it gives back the original text.

Encryption:

Decryption:

Conclusion:

This project successfully demonstrates the design, modeling, and functional verification of a hardware-level Vigenère Cipher cryptographic core using Verilog RTL. By transitioning the polyalphabetic substitution algorithm from software into a Register Transfer Level (RTL) architecture, the system achieves efficient parallel data processing driven by a dedicated Finite State Machine (FSM).

Future Scope:

As a future extension, the verified RTL design can be deployed onto an FPGA to demonstrate real-time encryption and decryption. This implementation will involve mapping the Verilog modules to physical hardware resources, utilizing onboard switches and buttons for user input, and displaying the cipher results via LEDs. Moving the design to hardware will allow for practical performance evaluation, synthesis optimization, and hands-on exposure to physical debugging tools.

References:

• Kahn, D. (1996). The Codebreakers: The Comprehensive History of Secret Communication. Scribner.
• Stinson, D. R. (2006). Cryptography: Theory and Practice (3rd ed.). Chapman & Hall/CRC.
• https://ieeexplore.ieee.org/document/9674565
• https://ieeexplore.ieee.org/document/9411383

Mentors:

• Arya Vishukumar (241EC108)
• Pavan Krishna Kumar (241EC141)
• Gowrinanda R (241EC215)

Mentees:

• Sanskruti Amit Shinde (251EC152)
• Rajath T N (251EE149)
• Chinmay Nair (251EE218)
• Nikitha Sarathy (251EE240)